Three-dimensional (“3D”) integrated circuits (“ICs”) are becoming more prevalent in semiconductor architecture and the increased density of chips, and the concomitant increased throughput of data, in these architectures presents new obstacles to operation of these systems. For wide bandwidth chips, where multiple data bits are required to be read at the same (or approximately the same) time, mismatch between the timing of these chips creates problems in obtaining an accurate reading of each data bit.
As is known in the art, any particular bit has an “eye opening” time associated with that bit. Typically, the “eye opening” time for any particular bit is the time between the leading edge of the bit and the falling edge of the bit. If the data bit is sampled during the “eye opening” time the value of the bit will be read correctly by the sampling device.
Typically, a reading clock pulse is ideally aligned with the center, or near the center, of the “eye opening” of a data bit so as to maximize the probability that the data bit will be read correctly. However, when there are multiple bits that are to be read on the same clock pulse and those multiple bits arrive at the sampling device at different times, the effective “eye opening” of the combined bits is reduced and/or is non-existent in extreme cases. These differences in arrival times of the various individual bits may result in a bit being read during a time other than during the “eye opening” of that bit resulting in a misreading of that bit. Consequently, errors in data occur which may lead to performance degradations and/or system failure.
Thus, there exists a need to solve the above deficiency.